1. Field of the Invention
The present invention relates to semiconductor-on-insulator (SOI) structures and more particularly methods for polishing the semiconductor layer of such structures.
2. Technical Background
To date, the semiconductor material most commonly used in semiconductor-on-insulator structures has been silicon. Such structures have been referred to in the literature as silicon-on-insulator structures and the abbreviation “SOI” has been applied to such structures. Silicon-on-insulator technology is becoming increasingly important for high performance thin film transistors, solar cells, and displays, such as active matrix displays. Silicon-on-insulator wafers consist of a thin layer of substantially single crystal silicon (generally 0.1-0.3 microns in thickness but, in some cases, as thick as 5 microns) on an insulating material. As used herein, SOI shall be construed more broadly, to include semiconductor materials other than and including silicon.
Various ways of obtaining SOI structures include epitaxial growth of silicon (Si) on lattice matched substrates. An alternative process includes the bonding of a single crystal silicon wafer to another silicon wafer on which an oxide layer of SiO2 has been grown, followed by polishing or etching of the top wafer down to, for example, a 0.1 to 0.3 micron layer of single crystal silicon. Further methods include ion-implantation methods in which either hydrogen or oxygen ions are implanted either to form a buried oxide layer in the silicon wafer topped by Si in the case of oxygen ion implantation or to separate (exfoliate) a thin Si layer to bond to another Si wafer with an oxide layer as in the case of hydrogen ion implantation.
The former two methods have not resulted in satisfactory structures in terms of cost and/or bond strength and durability. The latter method involving hydrogen ion implantation has received some attention and has been considered advantageous over the former methods because the implantation energies required are less than 50% of that needed for oxygen ion implants and the dosage required is two orders of magnitude lower.
Exfoliation by the hydrogen ion implantation method typically consists of the following steps. A thermal oxide layer is grown on a single crystal silicon wafer. Hydrogen ions are then implanted into this wafer to generate subsurface flaws. The implantation energy determines the depth at which the flaws are generated and the dosage determines flaw density. This wafer is then placed into contact with another silicon wafer (the support substrate) at room temperature to form a tentative bond. The wafers are then heat-treated to about 600° C. to cause growth of the subsurface flaws for use in separating a thin layer of silicon from the Si wafer. The resulting assembly is then heated to a temperature above 1,000° C. to fully bond the Si film with SiO2 underlayer to the support substrate, i.e., the unimplanted Si wafer. This process thus forms an SOI structure with a thin film of silicon bonded to another silicon wafer with an oxide insulator layer in between. This technique has been applied more recently to SOI structures wherein the substrate is a glass or glass ceramic rather than another Si wafer.
Once the SOI structure has been bonded to a thin film of silicon, it is typically necessary to polish the surface of the silicon layer to produce a layer having a substantially uniform thickness in order to facilitate the formation of thin film transistor (TFT) circuitry on the silicon. Conventional methods of polishing silicon wafers typically employ a piece-wise approach. That is, the thickness of the wafer as a function of location across the wafer is first determined. The wafer is then placed within an appropriate polishing jig, or holder, and the surface of the wafer polished. From time to time the wafer is removed from the holder and re-measured to determine the progress of the polishing step. Such a discontinuous method assumes that the polishing process is stable: i.e. the polishing parameters are consistent throughout the operation (e.g. temperature, slurry ph, wafer position, etc.). In reality, such parameters may be variable, affecting the results of the polishing process. This variability is exacerbated when applying the technique to large, thin sheets of glass substrate used in the manufacture of panels for electroluminescent displays. Glass sheets from which such panels are eventually cut can be several square meters or more in size, and be less than about one-half millimeter in thickness. The large size and thinness of the glass substrate results in the potential for sagging of the glass substrate, and difficulty accurately polishing a semiconductor layer on a surface thereof.